This invention relates generally to semiconductor manufacture, and specifically to an interconnect having laser machined contacts for electrically engaging external contacts on semiconductor components such as dice, wafers and chip scale packages.
Semiconductor components include external contacts that allow electrical connections to be made from the outside to the integrated circuits contained on the components. A semiconductor die, for example, includes patterns of bond pads formed on a face of the die. At the wafer level, the bond pads are used for probe testing the integrated circuits on the die. At the die level, the bond pads are used for testing, and also for making electrical connections, such as wire bonds, for packaging. Typically, the bond pads comprise planar aluminum pads, or alternately solder bumps on solder wettable pads.
Semiconductor packages, such as chip scale packages, also include external contacts. One type of chip scale package includes solder balls arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The solder balls can be mounted on a substrate attached to a face of the die contained in the package. Metal traces, or other conductive elements associated with the substrate, form separate electrical paths between the solder balls on the substrate, and the bond pads on the die.
with these types of semiconductor components, interconnects can be used to make electrical connections to the external contacts on the components. A wafer probe card is one type of semiconductor interconnect. The probe card makes electrical connections between external contacts on a wafer under test, and test circuitry associated with a wafer handler.
Another type of semiconductor interconnect is adapted to electrically engage unpackaged dice, or chip scale packages, packaged within a test carrier. The test carrier interfaces with a burn-in board, or other testing apparatus, adapted to apply test signals to the dice contained within the test carrier. This type of interconnect is described in U.S. Pat. No. 5,686,317 to Akram et al., and in U.S. Pat. No. 5,487,999 to Farnworth et al. A representative test carrier is described in U.S. Pat. No. 5,541,525 to Wood et al.
Yet another type of interconnect can be used to fabricate multi chip modules and other electrical assemblies. For example, a conventional multi chip module includes an interconnect formed of ceramic material or a glass filled resin. A multi chip module with a silicon interconnect is described in U.S. Pat. No. 5,578,526 to Akram et al.
In each of these applications the interconnect includes contacts adapted to electrically engage the external contacts on the semiconductor component. With a conventional needle probe card the contacts comprise probe needles. With an interconnect used with a test carrier as described above, the interconnect contacts can comprise projections formed on a silicon substrate and covered with a conductive layer. Interconnect contacts for multi chip modules can be configured to allow the dice to be flip chip mounted, or chip on board mounted, to the substrate.
One problem with making electrical connections to external contacts on semiconductor components is that with advances in semiconductor manufacture, the size and spacing of the external contacts is decreasing, and the total number of external contacts on a single component is increasing. A semiconductor die, or chip scale package, can include a hundred, or more, external contacts each having a diameter of only about 10 mils, and a pitch of only about 30 mils. A semiconductor wafer can include thousands of external contacts.
Making physical and electrical contact with small, densely spaced, external contacts on a semiconductor component requires small, densely spaced interconnect contacts. Also, the external contacts typically include a native oxide layer that must be penetrated by the interconnect contacts to make low resistance electrical connections. In addition, the interconnects must include separate electrical paths, such as conductive traces, to each interconnect contact. Because of the required size and spacing of the interconnect contacts complex electrical paths must be formed on the interconnects. Signal delays and high resistivity can result from complex routing of electrical paths on the interconnects. Electrical problems, such as cross talk, and parasitic signals, can also occur between the interconnect contacts, and between associated electrical paths on the interconnect.
The present invention is directed to an improved interconnect having contacts adapted to make reliable electrical connections to small, closely spaced external contacts on semiconductor components.
In accordance with the present invention, an improved interconnect for semiconductor components, and a method for fabricating the interconnect are provided. The interconnect, broadly stated, comprises: a substrate; patterns of interconnect contacts on a face of the substrate, configured to electrically engage external contacts on the components; and conductive members in the substrate for providing direct electrical paths from the interconnect contacts to a backside of the substrate.
The locations of the interconnect contacts matches the locations of the external contacts on the semiconductor components. For electrically engaging bumped external contacts, such as solder balls, the interconnect contacts comprise recesses covered with conductive layers. For electrically engaging planar external contacts, such as thin film bond pads, the interconnect contacts comprise projections covered with conductive layers. In either embodiment, the interconnect contacts can include penetrating members adapted to penetrate native oxide layers on the external contacts.
The conductive members of the interconnect comprise openings in the substrate and a conductive material, such as a metal, or a conductive polymer, deposited within the openings. The openings can be formed with a desired size and pitch using a laser machining process, and then insulated using a deposition process, or an oxidation process. The conductive members can also include external pads, and contact balls on the backside of the interconnect. The pads and contact balls facilitate electrical interface between the interconnect, and a mating electrical component, such as a test carrier, or a probe card fixture of a wafer handler. In addition, a pitch of the pads and contact balls on the backside of the interconnect, can exactly matches a pitch of the interconnect contacts on the face of the interconnect.
The interconnect can be used with the test carrier to provide a test system for testing singulated dice and chip scale packages. Alternately, the interconnect can be used with a wafer handler to provide a test system for testing semiconductor wafers. Still further, the interconnect can be used to construct chip scale packages, and electronic assemblies, such as multi chip modules.